In some digital signal processing systems, sample rate converters are used to effect a scaling of a digitally encoded video or audio signal, for example. A digitally encoded video or audio signal, includes an array of samples of the original signal. A decimator is used to remove sample values, if the signal is being down-converted. An interpolator is used to add sample values if the signal is being up-converted. To provide both up-scaling and down-scaling, the sample rate converters of some digital signal processing systems include both a decimator and an interpolator.
Decimators and interpolators are typically designed as part of digital filters. In this case, the resultant sample value is a weighted average of the samples in the vicinity of the sample. The number of samples used to determine the resultant weighted average is termed the number of “taps” of the digital filter. The general equation for an N-tap filter is given by:
            y      ⁡              (                  i          +          p                )              =                  ∑                  n          =          0                          N          -          1                    ⁢                        c          ⁡                      (                          n              ,              p                        )                          *                              x            ⁡                          (                              i                -                n                            )                                .                      )where x(i) . . . x(i-(N−1)) are the input samples at each tap of the N-tap filter, p is the phase, and c(n, p) is the weight associated with each input sample at the specified phase. a polyphase filter can be utilized to supply a variety of scale factors. Each phase of a P-polyphase filter corresponds to an integer multiple of 1/P of the output scale for down-sampling. Similarly, each phase of a P-polyphase filter corresponds to an integer multiple of 1/P of the input scale for up-sampling.
FIG. 1 shows a simplified block diagram of an up-sampling polyphase filter with P phase stages 110a-110p. Input samples 101 are input to each stage. If the output is an up-scaling by a factor of 1:P, the output of each stage 110a-110p is selected by switch 120, and P output values are provided in response to each input sample 101. After generating the P output values, the next input sample 101 is input, and another P outputs are generated. As a result, P output values are formed for each input sample, thereby providing an up-scaling by a factor of 1:P. For an up-scaling of Q:P, Q of the P stages are selected for output for each input sample. For example, if Q is three, every third stage 101a, 101d, etc. is selected for output for each input sample.
FIG. 2 depicts a simplified block diagram of a down-sampling polyphase filter with P phase stages 210a-210p. Input samples 201 are input to select stages via the switch 220. If the output is a downscaling by a factor of P:1, the output of all P stages 210a-p are combined by the adder 230, and a single output value 231 is generated in response to the P input samples 201. After generating the output value, another set of P inputs 201 generate the next output sample 231. As a result, one output value is formed for P input samples, thereby providing a downscaling by a factor of P:1. For a downscaling of Q:1, Q input samples 201 are input to select input stages 210a-210p and the output of these stages are combined by the adder 230 to produce the single output sample 231.
Polyphase filters are typically used to implement decimation and interpolation in a flexible yet computationally efficient way. A polyphase filter with N taps is typically designed as a single filter with N registers and some type of memory that is configured to store the N coefficients for each of the P stages. The N registers of the filter store the corresponding N coefficients for generating each required output.
In the traditional approaches, the decimation/interpolation filters are at a higher sample rate, that is, either before down-sampling or after up-sampling. Given that the down/up sampling ratio is Q, a polyphase filter structure splits the relating filtering into Q parallel stages operating at the lower sampling rate. In applications requiring very high operation speeds, this can be a crucial benefit. Furthermore, the polyphase structures are quite flexible if used, for example, in channelization applications.
However, as shown, typical up/down-scaling polyphase filters require N multipliers and M adders. A typical multiplier takes a significant amount of silicon area to implement in an Integrated Circuit (IC). For example, a typical size for a 22 bit multiplier implemented in 0.13 um CMOS technology is about 21,000 Sq. Microns. Likewise, a typical size for a 22 bit adder using a similar technology is about 670 Sq. Microns. As more complex functions are being integrated in a single IC, silicon area becomes an important consideration and limitation in designing such complex ICs.
Therefore, there is a need for an area-efficient polyphase filter for reducing expensive silicon area.